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Serial Communication Interface (SCI)
addresses. If SCKP is set and SSHTD is set, SCI Synchronous mode is equivalent to the SSI
operation in 8-bit data on-demand mode.
Note:
When data is written to a peripheral device, there is a two-cycle pipeline delay until
any status bits affected by this operation are updated. If you read any of those status
bits within the next two cycles, the bit does not reflect its current status. For details see
the DSP56300 Family Manual .
8.7 GPIO Signals and Registers
Three registers control the GPIO functionality of the SCI pins: Port E control register (PCRE),
Port E direction register (PRRE) and Port E data register (PDRE).
8.7.1 Port E Control Register (PCRE)
The read/write PCRE controls the functionality of SCI GPIO signals. Each of the PCRE[2–0] bits
controls the functionality of the corresponding port signal. When a PCRE[i] bit is set, the
corresponding port signal is configured as an SCI signal. When a PC[i] bit is cleared, the
corresponding port signal is configured as a GPIO signal. A hardware RESET signal or a software
RESET instruction clears all PCRE bits.
23
11
22
10
21
9
20
8
19
7
18
6
17
5
16
4
15
3
14
2
13
1
12
0
Note:
PE2/
SCLK
For bits 2–0, a 0 selects PEn as the signal and a 1 selects the specified SCI signal.
= Reserved. Read as zero. Write to zero for future compatibility.
Figure 8-8. Port E Control Register (PCRE X:$FFFF9F)
DSP56311 User’s Manual, Rev. 2
PE1/
TXD
PE0/
RXD
8-22
Freescale Semiconductor
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